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Design and Performance Comparison of X-Masking Models in DFT Applications

Publication Type : Conference Paper

Publisher : Elsevier

Source : Proceedings of the 8th International Conference on Communication and Electronics Systems, ICCES 2023

Url :

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2023

Abstract : VLSI technology advancements are rapidly evolving with the growing demands of human lifestyles. With all these advancements the circuit complexity and speeds are also increasing making the circuits even more difficult to test. From time to time various test schemes are being implemented to increase the quality of tests to bring more reliability to systems. Introduction of BIST was a major change in the testing method used till then. With the increase in complexity the occurrence of unknown values also increase. For the same different techniques are used as the presence of 'X' values significantly degrade the tests and test results. In this design a two stage X-masking model is implemented that is capable of masking the 'X' states that occur during the test cycle. Mostly in medical and space related systems require high level of accuracy where tolerance methods can reduce the efficiency of these systems. The design proposed here is an X-Masking model that monitors and masks the unknown values that occur during the test phase. The enhanced design is then compared for its utilisation and power consumption with a basic concept model for the masking. In the design scan chains are monitored for the occurrence of unknown values and they are masked using a two layered masking scheme preventing the propagation of unknown values into the MISR. The design is is simulated using Xilinx Vivado 2020.1 and implemented in Basys-3 FPGA board. © 2023 IEEE.

Cite this Research Publication : Bhakthavatchal Ramesh, Ajit Anaswar, Geethu R.S," Design and Performance Comparison of X-Masking Models in DFT Applications',

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