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Design of a Low Power, High Speed Double Tail Comparator

Publication Type : Conference Paper

Publisher : ICCPCT

Source : 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) (2017)

Url :

Keywords : ADC, analog to digital converter, Analog to digital converter(ADC), analogue-digital conversion, clock-gating, clock-gating techniques, Clocks, CMOS analogue integrated circuits, CMOS technology, Comparator, comparators (circuits), Computers, Delays, digital converter, Discharges (electric), dynamic comparator, dynamic comparators, dynamic regenerative double-tail comparator, electronic circuits, high speed double tail comparator, high-speed functioning, integrated circuit design, low-power electronics, MOSFET, Power Consumption, Power demand, regenerative comparator, size 180.0 nm, voltage 0.8 V

Campus : Coimbatore

School : School of Engineering

Center : Electronics Communication and Instrumentation Forum (ECIF)

Department : Electronics and Communication, Communication

Year : 2017

Abstract : In the fast moving digital world, it becomes imperative to constantly come up with innovation in digitization. The analog to digital converter is the second most widely used device in the world of electronic circuits. ADCs are composed of dynamic comparators. To overcome the challenges faced due to the digital change, improved versions of the conventional comparator design for high-speed functioning and low power consumption has been proposed. Area is another main factor when keeping in mind the design of these dynamic comparators. 180 nm CMOS technology and a constant supply voltage of 0.8V have been used. A conventional double tail comparator has been designed by adding transistors without hindering the functionality. This provides faster, more efficient modification of the comparator design. A new design for a dynamic regenerative double-tail comparator has been proposed which uses clock-gating techniques. This further reduces the power consumption and provides higher speed by reducing the delay time of the circuit

Cite this Research Publication : S. Aakash, Anisha, A., Das, G. J., Abhiram, T., and Dr. Anita J. P., “Design of a Low Power, High Speed Double Tail Comparator”, in 2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT), 2017.

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