Publication Type : Journal Article
Publisher : International Conference on Soft Computing and Signal Processing (ICSCSP-2018)
Source : Advances in Intelligent Systems and Computing, Springer Verlag, Volume 898, p.627-637 (2019)
ISBN : 9789811333927
Keywords : Add carry generator (ACG), Adders, Carry select adders, Common subexpression elimination, Digital signal processors, FIR filters, Half carry generator (HCG), Half summation generator (HSG), Impulse response, Reconfigurable architectures, Signal processing, Soft computing
Campus : Amritapuri
School : School of Engineering
Center : Amrita Innovation & Research
Department : Electronics and Communication
Year : 2019
Abstract : With increased complexity in digital circuits, efficient performance of involved circuitry has become the part and parcel of the digital signal processors (DSPs). In this paper, we have designed an efficient FIR filter for fixed and reconfigurable applications by embedding an area, and delay efficient carry select adder (CSLA), implemented by optimizing the redundancies in the logical operations in conventional and BEC-based CSLA. The proposed CSLA involves less area and delay than BEC-based CSLA and conventional CSLA. Here the carry operation is scheduled before the ultimate sum unlike the traditional method. Having desirably less output area and delay this becomes the best choice for FIR filter of transpose form. For the reconfigurable filter design, it is seen that the delay is reduced by 26.66%, and for MCM-based filter, the delay is reduced by 20.23%. The efficacy of the proposed design is accompanied by 15% reduction in area. © Springer Nature Singapore Pte Ltd. 2019.
Cite this Research Publication : S. Shah, Swaminadhan R., G.R., M. Reddy, V.S., R., and V.K., P., “Design of FIR filter architecture for fixed and reconfigurable applications using highly efficient carry select adder”, Advances in Intelligent Systems and Computing, vol. 898, pp. 627-637, 2019.