Publications

Abstract : During testing, the power dissipation is more than normal working. Among many reasons, one reason is due to a lot of transitions occur between bits of test patterns generated. The work advised here has a low power pattern generator for a built-in-self-test (BIST) design. The proposed design is a low power, improved version of a conventional linear feedback shift register (LFSR). The proposed designed named half-start-half-stop pattern generator (2HS-PG) is comprised of conventional LFSR, redesigned with add-on circuitry which brings down the total number of switching between the bits, results in low switching power during testing. Implementation of both conventional LFSR and 2HS-PG design are done in Cadence Genus tool, using 90 nm standard cell technology library and simulation is done in Xilinx ISE tool. Simulation result and analysis shows that more than 30% dynamic power reduction, when patterns are generated using proposed pattern generator.