Publication Type : Conference Paper
Publisher : 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) .
Source : 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) (2016)
Url : http://ieeexplore.ieee.org/document/7755102/?reload=true
Keywords : Analytical models, associativity, block size, cache configuration, cache design space exploration, Cache memory, cache parameters, cache size, cache storage, chip area, Design space exploration, energy consumption, Genetic algorithms, Hardware, Memory architecture, memory hierarchy, Multicore processing, Performance evaluation, replacement policy, Space exploration, system performance, write policies
Campus : Bengaluru
School : School of Engineering
Department : Computer Science
Year : 2016
Abstract : Cache memory plays a major role in memory hierarchy for improving the system performance. Cache configuration includes cache size, associativity, block size, replacement policy and write policies. Selection of different values for all these parameters decide the performance, energy consumption and chip area of the system for the given application. Finding the best cache configuration for application involves the cache design space exploration. Cache design space is time consuming because it contains all combination of cache parameters. This paper surveys different techniques to find the efficient design space aimed at reducing the design space time and provide good insight to researchers to explore further.
Cite this Research Publication : Bhargavi R. Upadhyay and Sudarshan, T. S. B., “Design space exploration of cache memory: A survey”, in 2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016.