Publication

Abstract : FPGA technology owes its rate of advancement to the tremendous amount of research work directed into the FPGA architecture development. There has been a constant striving for FPGA performance improvement from designers through innovative designs. For the purpose of performance enhancement evaluation due to the incorporation of a certain modification, say to the logic block or the routing fabric, a deep insight into the effects of such modification on the performance is needed. At present, this evaluation is carried out through computer aided design simulations which are labor-intensive and computationally-expensive experiments. A more scientific and rational method, based on the insight into the dependency of performance on architectural parameters makes the evaluation of new architectures more rapid and can be done even before a CAD tool is developed. This paper presents a comparison between the results obtained using the conventional CAD flow method as well as using an analytical model which describes relationships between architecture and logic. The model is based fundamentally on Rent's rule. In particular, the model draws a relationship between architectural parameters and the area efficiency of an FPGA. The simplicity of the model's equations renders it an effective tool for FPGAs architects to better comprehend and usher the development of modern FPGA architectures.