Publications

Abstract : in the current scenario, the development of portable devices is mounting significantly. As a result, the designers have to restrict the high power utilization in these portable devices. Digital multiplication is most predominantly used arithmetic operations in several ranges of applications like discrete cosine transform, digital signal processing, and in a variety of scientific arithmetic circuits. Overall working of the VLSI system is primarily based on the multiplier. Previously, proposed an agingaware multiplier design with Adaptive Hold Logic (AHL) circuit. In this scheme, the negative bias temperature instability effect takes place in case if pMOS transistor undergoes negative bias, thus increases the delay of the pMOS transistor, and at the same time considerably reduces the multiplier speed. Accordingly, in case of positive bias temperature instability takes place when nMOS transistor undergoes positive bias. Owing to these effects, transistor speed is reduced and timing violation happens as a result of system breakdown. Therefore, the circuit is important to design high performance multipliers for signed multiplication. In this research work, an aging-aware multiplier design with novel Adaptive Hold Logic (AHL) circuit proposed with the use of 8-bit booth multiplier. This multiplier is potential enough to provide better throughput through the variable latency and can also finetune the AHL circuit to lessen performance degradation, specifically owing to the aging effect. Furthermore, this architecture can be implemented to column multiplier, the inputs to the full adder cells are given by means of utilization of hardware applied with a condition without buffers. The design of booth multiplier is capable of providing low power utilization through AHL circuit and in addition reduces the timing violations. At last, the experimental results found that the booth multiplier with AHL can provide low power and delay as compared to Column bypass multiplier and Column multiplier without buffer. In addition, the proposed architecture with column- bypassing multipliers can achieve up to 81.19% performance improvement as compared with Column bypass multiplier and Column multiplier without buffer.