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Publication Type : Conference Paper
Publisher : Institute of Electrical and Electronics Engineers Inc.,
Source : 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, Institute of Electrical and Electronics Engineers Inc., p.478-482 (2015)
ISBN : 9781479987917
Keywords : Capture, Don't-cares, Fault coverages, Filling, Information science, Integrated circuit testing, Shift, Switching activities, Test power, Transition faults, X-filling
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2015
Abstract : Since VLSI technology has become ubiquitous in today's world, this field is a prime candidate for power reduction. Tremendous growth in chip density and reduction in dimensions contribute to an escalation in clock rate. Delay faults are detected using at-speed scan testing. This paper proposes a novel method to achieve power reduction during scan test by using x-filling. In this paper, ISCAS′89 benchmark circuits have been used with an industrial 90nm technology. The tools used were Synopsys TetraMAX and Synopsys Design Compiler. Experimental results show a considerable reduction in average shift power and average capture power. © 2015 IEEE.
Cite this Research Publication : V. Sinduja, Raghav, S., and Dr. Anita J. P., “Efficient don't-care filling method to achieve reduction in test power”, in 2015 International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015, 2015, pp. 478-482.