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Publication Type : Conference Paper
Publisher : 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI),
Source : 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), IEEE, Bangalore, India (2018)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2018
Abstract : In Network on chip the key performance is that of a router. The main components of the router are the input-port buffers, arbiter and the crossbar switch. There are architectures such as link-list based router (CDVC), efficient dynamic VC(EDVC) architecture etc. which are used to organize the router in an efficient way to enhance its performance, but there are a few drawbacks such as low operating frequency and higher power consumption. In this paper, a model, which effectively combines some concepts of the CDVC like FIFO based write pointer and EDVC mechanism's fast read pointer is used, along with a new proposed write mechanism. Clock gating technique and latch-based pipelining is introduced in the router architecture, all of which contribute to the increase in the operating frequency of the system. For the proposed model the power is decreased by 47% with respect to CDVC and 16% with respect to EDVC and operating frequency is increased by 70% on an average.
Cite this Research Publication : P. Avani and S. Agrawal, “Efficient Dynamic Virtual Channel Architecture for NoC Systems”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), Bangalore, India, 2018.