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Publication Type : Conference Paper
Publisher : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech)
Source : 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), IEEE, Kolkata, India (2020)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2020
Abstract : The utilization of Floating Point (FP) numbers had increased due to the complications of recent Digital signal processing (DSP) applications. In field-programmable gate arrays, to execute digital signal applications, HUB formats are used. By using this floating-point HUB format, the logic of rounding can be eliminated. The HUB format lessens the resource utilization and increases the speed of floating-point units. At the same time, it is providing the equivalent accuracy when compared to the conventional formats. In this paper, a double path floating-point HUB adder with Spurious Power Suppression Technique (SPST) is proposed. This adder is coded in Verilog, simulated and synthesized using Xilinx ISE 14.2 and Virtex-6 FPGA, xc6vlx240 is used to implement it. The performance of proposed adder is analysed and compared with existing double path HUB adder. The proposed HUB adder with SPST is improved with respect to power and delay as compare to existing HUB adder.
Cite this Research Publication : M. Lahari and S. Agrawal, “Efficient Floating-Point HUB Adder For FPGA”, in 2020 4th International Conference on Electronics, Materials Engineering Nano-Technology (IEMENTech), Kolkata, India, 2020.