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Exploring hierarchical, cluster based 3D topologies for 3D NoC

Publication Type : Conference Proceedings

Publisher : Procedia Engineering

Source : Procedia Engineering, Volume 30, Coimbatore, p.606-615 (2012)

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Keywords : 3D NoC, Buffer sizes, Communication, Electric network topology, Energy dissipation, IP blocks, latency, Microprocessor chips, network diameter, Routing algorithms, Systems analysis, Three dimensional, Topology, traffic rate, TSVs, VLSI circuits

Campus : Coimbatore

School : School of Engineering

Department : Mathematics

Verified : Yes

Year : 2012

Abstract : Network-on-Chip (NoC) has been recognized as an effective solution for complex on-chip communication problems faced in System-on-Chips (SoCs). Network topology, switching mechanism and routing algorithms are the key research area in NoC. In recent years, since the inception of Through-Silicon-Vias (TSVs) to realize vertical channel, 3D stacked NoC architecture attracts a lot of interest as it offers improved performance and shorter global interconnect. In this paper, two clustered 3D network topologies (3D-ST and 3D-RNT) and hierarchical, cluster based routing algorithms are presented. Experimental results on various parameters like latency, drop probability and energy dissipation are compared for the two topologies. It is demonstrated from the analysis that 3D-RNT is an appropriate candidate for 3D NoC provided interlayer communications are not very frequent.

Cite this Research Publication : Na Viswanathan, Paramasivam, Kb, and Dr. Somasundaram K., “Exploring hierarchical, cluster based 3D topologies for 3D NoC”, Procedia Engineering, vol. 30. Coimbatore, pp. 606-615, 2012.

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