Programs
- Ph. D. in Mechanical Engineering -
- B.Tech. in Artificial Intelligence (AI) and Data Science (Medical Engineering) - Undergraduate
Publication Type : Journal Article
Source : Proceedings of the International Conference on Trends in Electronics and Informatics, pp. 412-417, 2019
Url : https://ieeexplore.ieee.org/abstract/document/8862751
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract : As the complexity of the digital circuits increases there should be a check on its functionality in a more exhaustive way. So here comes the need for test pattern generation technique to detect the presence of the faults and to obtain the test patterns. The switching activity in digital circuits may overheat the circuit due to which unwanted responses may occur. This may lead to a high power consumption, so it is necessary to reduce the power. The proposed paper includes generation of test patterns and a technique for test power reduction in VLSI. The results have been validated using ISCAS'85 and ISCAS'89 benchmark circuits.
Cite this Research Publication : Kumar, C.N., Madhumitha, A., Preetam, N.S., Gupta, P.V., Anita, J.P, “Fault diagnosis using automatic test pattern generation and test power reduction technique for VLSI circuits”, Proceedings of the International Conference on Trends in Electronics and Informatics, pp. 412-417, 2019.