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Publication Type : Conference Paper
Publisher : 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)
Source : 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), IEEE, Coimbatore, India (2015)
Keywords : Adders, area reduction, complex multiplication, Complexity theory, Delays, Fast Fourier transform (FFT), Fast Fourier transforms, field programmable gate array platforms, Field programmable gate arrays, hard wired Twiddle factor storage, high throughput feed forward architecture, IFFT, inverse fast Fourier transform, Inverse fast Fourier transform (IFFT), Inverse transforms, Logic design, Parallel processing, pipelined parallel architecture, Pipelining, radix-2, switching circuit, Synopsys design compiler, Table lookup, time complexity reduction, Tin, TSMC library, Very large scale integration, VLSI
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Verified : No
Year : 2015
Abstract : This paper presents a novel approach to develop pipelined architectures for fast Fourier transform (FFT) and Inverse fast Fourier transform (IFFT). For reducing area and time complexity, the architectures use hard wired Twiddle factor storage and new switching circuit for complex multiplication and that is employed in four point FFT/IFFT architectures. Pipelined Architectures for complex valued fast Fourier transform and Inverse fast Fourier transform are derived. This projected design is intended based on feed forward designs and may be extended to any radix 2supn/sup based FFT/IFFT algorithm to extend the throughput. The projected FFT/IFFT design was synthesized by Synopsys design Compiler using the TSMC 90-nm library, and also the projected designs provide less latency and high Throughput than the reference FFT design. The design also synthesized for various Xilinx field-programmable gate-array platforms that also shows comparable results.
Cite this Research Publication : Paramasivam C., “High throughput feed forward pipelined parallel architecture for FFT and IFFT”, in 2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS), Coimbatore, India, 2015.