Publication Type : Conference Paper
Publisher : Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology
Source : Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, p.538-542 (2009)
ISBN : 9781424445196
Keywords : Cache design, Clock frequency, Clocks, CMOS, CMOS circuits, Computer science, Design, Dual-edged clock, Dynamic Power, Dynamic power dissipation, Electric power utilization, energy consumption, Energy management, Information technology, ON dynamics, Operating frequency, Power efficiency, Power efficient, Power managements, Power requirement, Processor cache, Verilog HDL
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2009
Abstract :
Dynamic power dissipation is a major field where various researches have been held to reduce the energy consumption in present clocked systems. Here we discuss the various tiers of power management in design followed by a treatise on dynamic power dissipation in CMOS circuits and power efficient cache designs under research. We further propose a technique in reducing the clock frequency of circuits without compromising the performance. This is achieved by using a dual-edged clock for the operation, allowing the operating frequency to be halved, which immediately translates into a tremendous gain in power efficiency. The applications of this technique in processor caches are also studied. The designs proposed herein were implemented using Verilog HDL and the power requirements analyzed using Xilinx XPower 10.1. Experimental results and the conclusions drawn are included. © 2009 IEEE.
Cite this Research Publication : Rajesh Kannan Megalingam, Krishnan, N., V. Ashok, A., and Arunkumar, M., “Highly Power Efficient, Uncompromised Performance Cache Design Using Dual- Edged Clock”, in Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, 2009, pp. 538-542.