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Hybrid Architecture for Sinusoidal/Non sinusoidal Transforms

Publication Type : Journal Article

Publisher : Springer

Source : Circuits, Systems, and Signal Processing, Volume 41, Issue 7, Jul 2022, pp 3903–3930

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Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Year : 2022

Abstract : Applications such as multimedia and system on chip require multiple transforms for processing various types of signals such as text, audio, image and video. Hybrid architectures supporting multiple transforms improve the overall performance of the system. In this work, reduced form of discrete Fourier transform (DFT), discrete cosine transform (DCT), discrete sine transform (DST) and opitimized form of discrete Hartley transform (DHT) and Haar Wavelet Transform (HWT) are proposed to design a hybrid architecture that supports multiple discrete transforms of order-8. An architecture is designed by considering the computational needs across transforms with a blend of concurrent and sequential computations through mode control. In existing literature limited work is reported on hybrid architectures for sinusoidal and non-sinusoidal transforms DFT, DCT, DST, DHT and HWT. In this paper authors propose a pipelined and parallel architecture for multiple 8-point transforms which is capable of producing the outputs in two modes, namely, sequential and concurrent. Novelty of the approach is to have a provision to select an appropriate transform for an application and also choose multiple transforms as per requirement. Since, these transforms are used in various applications, the proposed approach is useful in heterogeneous systems requiring output from multiple transforms either in parallel or sequential mode. A prototype of the proposed architecture is implemented using Xilinx ISE tools with the target FPGA as Virtex 6 xc6vlx760ff1760-2. The results are verified using Matlab implementation with mean square error of 2.2497 × 10–9. Compared to the standalone architectures and other similar architectures, the proposed hybrid architecture has shown improvement in area-time complexity with a throughput of at least 4 × due to increased level of parallelism and pipelining.

Cite this Research Publication : Mamatha I, ShikhaTripathi, Sudarshan TSB., ‘Hybrid Architecture for Sinusoidal/Non sinusoidal Transforms”, Circuits, Systems, and Signal Processing, Volume 41, Issue 7, Jul 2022, pp 3903–3930

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