Programs
- M. Tech. in Automotive Engineering -
- Clinical Fellowship in Laboratory Genetics & Genomics - Fellowship
Publication Type : Conference Paper
Publisher : National Power Electronics Conference
Source : National Power Electronics Conference NPEC-2015, IIT Bombay December 21-13, 2015
Url : https://www.ee.iitb.ac.in/npec/Papers/Program/NPEC_2015_paper_70.pdf
Campus : Chennai
School : School of Engineering
Center : Amrita Innovation & Research
Department : Electronics and Communication
Verified : Yes
Year : 2015
Abstract : Generally phase lock loop (PLL) is used for grid synchronization and also to evaluate the phase angle and frequency for grid interfaced renewable energy sources (RES). During harmonics in the grid voltage, conventional PLL design methods have more steady state error in the tracked frequency and phase. This paper proposes an improved phase estimation method based on sliding discrete Fourier transform (SDFT) and sliding Goertzel discrete Fourier transform (SGDFT) techniques. The SDFT based PLL has additional number of multiplications and computation process is reduced by using SGDFT PLL by providing a pole-zero pair in the system such that the performance of the PLL is improved. The proposed techniques are mathematically explained and simulated and finally the acquired results are compared with each other and result shows that the SGDFT PLL has less computation process and accurately tracked the phase and frequency with less total harmonic distortion (THD) of the estimated fundamental signal under harmonics grid in the voltage.
Cite this Research Publication : S.A.Lakshmanan, B.S.Rajpurohit, A. Jain, “ Improved PLL design based on SDFT and SGDFT for Grid Interfaced Renewable Energy Sources under Harmonic Condition,” National Power Electronics Conference NPEC-2015, IIT Bombay December 21-13, 2015