Publication Type : Journal Article
Publisher : Journal of Computational and Theoretical Nanoscience
Source : Journal of Computational and Theoretical Nanoscience, Volume 13, Number 11", publication date ="2016-11-01T00:00:00, p.8879-8884 (2016)
Url : https://www.ingentaconnect.com/content/asp/jctn/2016/00000013/00000011/art00151
Campus : Coimbatore
School : School of Engineering
Center : Amrita Innovation & Research
Department : Electronics and Communication
Verified : Yes
Year : 2016
Abstract : Timing analysis is an important aspect in chip design which has the major attributes as speed and accuracy. Static Timing Analysis (STA) and Statistical Static Timing Analysis (SSTA) are the two existing timing engines to serve this task. The data handling in SSTA is a crucial task as it determines the speed or arrival time calculation. Circuits are converted as timing graphs and refactoring technique is applied to reduce the accuracy reduction caused by the replicated literals. We have developed a new methodology which uses refactoring technique with a view to speed up the computation. Parallel processing reduces the execution time. Certain nodes of the graph require serial processing. Hence an efficient data handling methodology was adopted on timing graphs. The proposed model was tested on ISCAS 85 benchmark and an increase in speed was obtained. A speed of 2×was achieved for parallel processing and this idea can be further used in criticality computation.
Cite this Research Publication : Ramesh S. R. and Jayaparvathy, R., “Improved Statistical Static Timing Analysis Using Refactored Timing Graphs”, Journal of Computational and Theoretical Nanoscience, vol. 13, pp. 8879-8884, 2016.