Publication Type : Conference Paper
Publisher : ICWET 2010
Source : ICWET 2010 - International Conference and Workshop on Emerging Trends in Technology 2010, Conference Proceedings, Mumbai, Maharashtra, p.874-879 (2010)
ISBN : 9781605588124
Keywords : Clocking schemes, Clocks, Core area, Data path design, Data paths, Datapath, Design, Low Power, Low power VLSI circuits, Low-power consumption, Nanotechnology, Pipeline processing systems, Power Consumption, Power reductions, Processor design, Research activities, VLSI circuits
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2010
Abstract :
Low power VLSI circuit design is a core area for current research activities. Power reduction without compromising the performance is the vital concern for processor design. In this paper, we apply a new clocking scheme as in [1] that can be used to reduce the power consumption in a processor datapath. We have mainly focused on implementing the pipelined DLX processor datapath in HDL using two different clocking schemes as in [1] and analyzed the power consumption. We have adopted the method which uses dual edge triggered clock that can decrease the power consumption of a pipelined datapath considerably, without sacrificing the throughput of the CPU. Finally, we have given the experimental results which confirm the low power consumption of the DLX processor datapath. Copyright 2010 ACM.
Cite this Research Publication : Rajesh Kannan Megalingam, Hassan, S., Rao, T., Mohan, A., and Perieye, V., “Low Power Analysis of DLX Processor Datapath using a Novel Clocking Scheme”, in ICWET 2010 - International Conference and Workshop on Emerging Trends in Technology 2010, Conference Proceedings, Mumbai, Maharashtra, 2010, pp. 874-879