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Low Power Implementation of Advanced Encryption Standard using Efficient Shift Registers in 45 nm Technology

Publication Type : Conference Paper

Publisher : 3rd International Conference on Communication and Electronics Systems (ICCES 2018)

Source : 3rd International Conference on Communication and Electronics Systems (ICCES 2018) (2018)

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Year : 2018

Abstract : Security is the most important aspects of Internet of Things (IoT). The popularity of IoT increased the need of RadioFrequency Identification (RFID) chips and smart cards that are energy efficient and more secure against attacks. Lightweight encryption circuit is essential for any IoT application, which is required to be energy and area efficient. This paper introduces an AES implementation using energy efficient shift register with ADOC and RTPG gating technique which improves the efficiency of the AES implemented design. Comparison is done with the current AES implemented designs with respect to power, area and delay. The proposed AES design shows 29.32 percent improvement in power consumption over register renaming based AES design.

Cite this Research Publication : Y. Singh Sikarwar and Dr. N.S. Murty, “Low Power Implementation of Advanced Encryption Standard using Efficient Shift Registers in 45 nm Technology”, in 3rd International Conference on Communication and Electronics Systems (ICCES 2018), 2018.

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