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Low power NoC buffer protection using error correction code

Publication Type : Conference Paper

Source : AIP Conference Proceedings

Campus : Bengaluru

School : School of Engineering

Year : 2023

Abstract : Network-on-Chip (NoC) is most widely used as a communication framework to connect various Intellectual Properties (IPs) in an Integrated Circuit (IC). As technology scales down, buffers present in NoC Router are more prone to Multiple Cell Upsets (MCUs). To overcome this, Error Correction Code (ECC) is introduced in NoC Router. Inclusion of ECC increases the number of redundant bits stored in NoC buffer for error correction. This impacts the area, operational power and the delay of the NoC router. The work discusses about correction of 6-adjacent error bits in the data stored in the NoC buffer with the help of optimized buffer scheme. The work proposes a new method to efficiently design the H-Matrix, which is used to construct an ECC, so as to reduce the total buffer area, power overhead and the delay constraints arising out of the ECC. The buffer scheme is implemented using this ECC for 16-bit data. The results obtained is compared with similar other ECC's which uses the same or lesser number of redundant bits. The synthesis result shows that the power requirement and delay are reduced by 7\ and 2\ respectively with higher error correction capacity, when compared with Triple Adjacent Error Correction (TAEC) Code.

Cite this Research Publication : T. Katheresh I. and M. Vinodhini,” Low Power NoC Buffer Protection using Error Correction Code ”, AIP Conference Proceedings. , 2023, 2725, 040005

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