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Making wide-issue VLIW processors viable on FPGAs

Publication Type : Journal Article

Publisher : ACM Transactions on Architecture and Code Optimization (TACO)

Source : ACM Transactions on Architecture and Code Optimization (TACO), ACM, Volume 8, Number 4, New York, NY, USA , p.33 (2012)

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Keywords : Multi-port memory, Resource efficiency, Soft-processor

Campus : Bengaluru

School : School of Engineering

Department : Computer Science

Year : 2012

Abstract : Soft and highly-customized processors are emerging as a common way to efficiently control large amount of computing resources available on FPGAs. Yet, some processor architectures of choice for DSP and media applications, such as wide-issue VLIW processors, remain impractical: the multi-ported register file makes a very inefficient use of the resources in the FPGA fabric. This paper proposes modifications to existing FPGAs to make soft-VLIW processor viable. We introduce an embedded multi-ported RAM that can be customized to match the issue-width of VLIW processors. To ascertain the benefits of this approach, we map an extensible VLIW processor onto a standard FPGA from Xilinx. For the register file implemented in the modified FPGA, the area occupied is at least 102× smaller and the dynamic power is reduced by 41% as compared to the implementation using configurable logic blocks in existing standard FPGAs. A subset of this embedded multi-ported RAM can also be used for mapping the register file in soft-RISC processors. For the soft-RISC processor, the register file in the modified FPGA is at least 22× smaller than its equivalent that uses configurable logic blocks and 1.5× the size in comparison to the implementation using block RAMs. Reduction of routing area and the maximum net length is about 39% and 51% respectively for RISC processors. As a result, this approach works towards enhancing soft-processor density in FPGAs by orders of magnitude.

Cite this Research Publication : Dr. Madhura Purnaprajna and Ienne, P., “Making wide-issue VLIW processors viable on FPGAs”, ACM Transactions on Architecture and Code Optimization (TACO), vol. 8, p. 33, 2012.

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