Publication

Abstract : The importance of standard cell library design methodology is growing with very-large-scale integration (VLSI) technology advancement due to its usage in VLSI EDA synthesis flows. In this paper, to best of our knowledge and information in any published literature no systematic method of standard cell and creating appropriate co-laterals. In this paper the standard cell design methodology, layout topology, methodology for creating characterized timing table has been developed using 250 nm technology GPDK. This method can be easily reused in deep sub-micron technology for appropriate co-laterals. In addition a new methodology of reusing standard cell for full custom design has been proposed in this paper