Publications

Abstract : Physical Unclonable Functions (PUFs) present a fresh answer to security concerns due to their intrinsic unpre-dictability. However, coming to newly created PUF architecture for a specific application or fitting into an existing architecture which suites the application is a tedious task, that necessitates a set of specific features tailored to the application. Physical Unclonable Functions (PUFs), which take advantage of inevitable and non-reproducible variances in integrated circuits to generate responses unique to individual PUF devices, are emerging as attractive options for keyless security primitives. The study of this fundamental PUF primitive allows for advancement in the field of hardware security. Prior to taking control of the design, it is necessary to assess the requirements and choose a specific PUF architecture. Area, Power, and Delay could be used to parameterize the requirements. Specific hardware security parameters such as uniqueness, dependability, and so on are important to consider while making a decision. The number of bits needed for a perfect CRP and specification is also crucial. The goal of this research is to investigate several delay-based PUFs for FPGAs and analyse them using Matlab and Vivado simulations with appropriate parameters. Researchers and other application developers can use the findings to select the best PUF design and expand the range of PUF - based protocols and security applications. In this work a qualitative analysis of resource utilization and uniqueness(simulated) for various delay based PUF architectures were done.