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Power Estimation in 6T Sram Using Recovery Boosting

Publication Type : Conference Paper


Source : M.A.M COLLEGE OF ENGINEERING, India from 16-Mar-2012 to 17- Mar-2012

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Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Year : 2012

Abstract : Static RAM cells are widely used for industrial and scientific subsystems, automotive electronics, etc .The power consumption of SRAM values depend on how frequently it is accessed. It can be power-hungry as dynamic RAM, when used at high frequencies. Integrated circuits consume higher watts at full bandwidth. In non-volatile SRAM and asynchronous SRAM, Power consumption limits its application. Power consumption of SRAM is due to yield loss by considering NBTI. It is due to interface traps generated when device is stressed .In previous techniques, SRAM cells aim to balance the degradation of two PMOS devices by attempting to keep their inputs at logic 0 exactly 50% of time. The proposed technique that allows PMOS device as memory cell to be put into recovery mode by slight modification. Recovery boosting technique in SRAM provides 56% improvement in the static noise margin for issue queue and its Simulations to verify its functionality and quantify areas and power consumption.

Cite this Research Publication : BALA VISHNU J, "POWER ESTIMATION OF 6T SRAM USING RECOVERY BOOSTING" presented in a National level conference on INNOVATIONS IN POWER-ELECTRONICS CONTROL SYSTEMS, organized by M.A.M COLLEGE OF ENGINEERING, India from 16-Mar-2012 to 17-Mar-2012.

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