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Power Reduction by Clock Gating Technique

Publication Type : Conference Proceedings

Publisher : Elsevier

Source : International Conference on SMART GRID Technologies, Procedia Technology 21, Elsevier, p.631-635 (2015)

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Keywords : Clock gating; Low power; Sequential Benchmark circuits

Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Year : 2015

Abstract : A continuous increase in the number of transistors mounted on a single chip brings about the need for power optimization. In this era, where technologies such as smart grid are developed, scope for power optimisation is increasing. Smart grid is an integration of essential building blocks such as sensor system, control units into existing power systems which could be implemented as a Silicon on Chip (SoC) in Very Large Scale Integration (VLSI) circuits. VLSI circuits can be both combinational and sequential. In sequential circuits clock is the major source of dynamic power consumption. The technique of clock gating is used to reduce the clock power consumption by cutting off the idle clock cycles. In this paper, we propose aVHDL-based technique, to insert clock gating circuit and also the dynamic power due to this is estimated. This model has been implemented onto ISCAS’89 sequential circuits that have been compiled using Modelsim Altera 13.1, and the Xilinx ISE tool is used to simulate and analyze power. The results show that the dynamic power is reduced for the sequential benchmark circuits considered.

Cite this Research Publication : N. Srinivasan, Prakash, N. S., Shalakha, D., Sivaranjani, D., Dr. Bala Tripura Sundari B., and , “Power Reduction by Clock Gating Technique”, International Conference on SMART GRID Technologies, Procedia Technology 21. Elsevier, pp. 631-635, 2015.

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