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PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry

Publication Type : Conference Paper

Publisher : IEEE

Source : Proceedings of VLSID Feb 2021, Assam, India

Url :

Campus : Amritapuri

School : School of Computing

Verified : No

Year : 2021

Abstract : Spiking Neural Networks (SNN) have gained relevance in recent times, due to their ability to mimic the biological nature to communicate and process sparse asynchronous binary signals in a massively parallel fashion. SNN based neuromorphic hardware exhibits highly desired favourable properties such as low power consumption, fast inference, and event-driven information processing. A recognized challenge of standard SNN neuron models is their limited capabilities in biological applications, such as applying neural networks to study network responses arising from variations pertaining to damage, external influence or disruptions in channel transfer dynamics. This paper presents Pre-Synaptic Neuronal Circuit (PreSyNC), a high performance hardware realization of an input-specific presynaptic region of a generic neuron, without abstraction of primary intra-neuronal parameters. PreSyNC is configured to operate on three precision modes: IEEE 754 single precision, double precision and the recently developed universal number posit number system. The developed hardware design is compared to current standards of SNN neuron models as well as biological models in terms of flexibility, resource efficiency and damage modelling capability. Error margins as low as 0.9 % were obtained and suggest the capability of our hardware in handling applications involving large scale neuron networks. These architectures are synthesized on 45 nm process technology where they all operate at a minimum frequency of approximately 1GHz. The three precision modes are compared based on power, accuracy, and sensitivity handling and are expected to benefit implantation oriented applications such as neural prosthesis and Human-Computer Interaction (HCI). The posit-based implementation outperforms the rest of the operating modes in terms of RMS error, while having 26.3 % less area and 25.2 % less power consumption compared to double precision implementation. These new architectures can be expanded in the fut...

Cite this Research Publication : R. Chatterjee, S. Chowdhury, S. Mondal; A. Raha, J. L. Paluh, and A. Mukherjee, “PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry”, Proceedings of VLSID Feb 2021, Assam, India

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