Publications

Abstract : High level synthesis (HLS) tools enable the use of high level languages such as C, C++ and SystemC for VLSI design. This simplifies the programming task and also allows the programmers to apply various pragmas or synthesis directives for controlling the hardware design parameters. Since these directives can take multiple values and also can be applied in many places for ASIC and FPGA designs, the design space grows exponentially making the design space exploration time consuming. Predicting Pareto optimal designs by performing HLS for minimum possible designs has been a driving force to bring in the learning techniques such as Random forests and Gaussian Process models. However, these techniques suffer from scalability issues in large design space or are ineffective in utilizing the prediction uncertainty information for model refinement. We propose a novel active learning approach for design space exploration (Q-PIR) based on the theory of Quantile Regression Forests. Our technique uses the conditional quantiles and prediction intervals to build the region of prediction uncertainty for model refinement and Pareto front discovery in the objective space of area and latency. Through experimental evidence across HLS specific benchmarks, our approach demonstrates better performance in Pareto front discovery than the state-of-the art approaches.