Publication Type : Conference Paper
Publisher : IEEE, EDAPS-2018
Source : IEEE, EDAPS-2018, Chandigarh, India, 2018.
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2018
Abstract : .. The results obtained using MATLAB R2010a operating on HP 64-bit Intel i5 processor with clock speed of 2.53 GHz, are compared with HSPICE using the W-element model. The typical interconnect parameters  for simulations of single RLC interconnect and H-tree is given in Table 1 Tables 2 and 3 give the comparisons of 50 % delay values obtained using existing Eudes model , proposed models and HSPICE for various lengths, ramp input rise times, source resistances, parasitic capacitances, and load capacitances. These tables also include the error percentages of 50 % delays with respect to HSPICE results, which are measured from time domain responses of the existing model and proposed Table 3 indicate that, for H-tree 4th node the proposed MPTA-based model has worst case50 % delay error of 5.73 %, while the proposed MPTA-based model with S & S method has an error of 3.94 %. ...
Cite this Research Publication : Vrinda K and Dr. Dhanesh G. Kurup, “Rational Function Approximation of Parallel Coupled line Interconnects in Integrated Circuits”, in IEEE, EDAPS-2018, Chandigarh, India, 2018.