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Publication Type : Journal Article
Publisher : International Conference on Intelligent Computing (ICIC) 2018
Source : International Conference on Intelligent Computing (ICIC) 2018, 2018.
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2018
Abstract : Decrease in size of IP cores, the Network-On-Chip (NOC), which is used to interconnect them, becomes more complex. NOC employ Network Interface (NI), routers and links. Chip process technology is shrinking day by day resulting in design complexities. This rises the chances of NOC becoming faulty and corrupting the packets transmitted through it. Further NOC has great influence on the complete system performance. Despite the fact that the NOC outperforms the traditional bus based interconnects, NOC faces problems with the usage of router pipeline stages. Generic pipelined router consists of Routing Computation (RC) stage, Virtual channel Allocator (VA) stage, Switch Allocator (SA) stage and CrossBar (CB) stage. These routers are more liable to hard faults and soft-errors. Hence, incorporation of an error tolerant technique to the pipeline stages is required. However, these results in area, power and delay overhead. In this paper, we proposes Route-On-Fly NOC router architecture with Soft-error tolerance (ROFNS), an optimized pipeline router with tolerance to soft errors. In addition, optimized VA stage to achieve overall reduction in area and delay penalty is also proposed. Implementation results show that there is 70%, 3% and 16% reduction in area, power and delay respectively when compared to Soft-error Tolerant NOC Router (STNR).
Cite this Research Publication : Sandeep, D., Vinodhini, M., Murty, N.S., “Route-on-fly network-on-chip router design with soft-error tolerance”, Journal of Computational and Theoretical Nanoscience, 2020, 17(1), pp. 329–333.