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Run-time reconfigurability in embedded multiprocessors

Publication Type : Journal Article

Publisher : ACM SIGARCH Computer Architecture News

Source : ACM SIGARCH Computer Architecture News, ACM, Volume 37, Number 2, New York, NY, USA , p.30–37 (2009)

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Campus : Bengaluru

School : School of Engineering

Department : Computer Science

Year : 2009

Abstract : To meet application-specific performance demands, architectures are predominantly redesigned and customised. Every architectural change results in huge overheads in design, verification, and fabrication, which together result in prolonged time-to-market. As an alternative, configurable architectures provide easy adaptability to different application domains in place of costly redesigns. To deal with application changes and custom requirements, a method of configuring and reusing the basic building blocks within processors is developed. Additionally, this enables co-operative multiprocessing. In this paper, a runtime reconfiguration mechanism for embedded multiprocessor architectures is proposed as a method to introduce customisations in the post-fabrication phase. A method of application description in conjunction with a flexible reconfigurable multiprocessor template is presented. Finally, the costs and benefits of this approach are analysed for computationally intensive algorithms used in digital signal processing. The impact of application specific characteristics on execution time, power consumption, and total energy dissipation are analysed.

Cite this Research Publication : Dr. Madhura Purnaprajna, Porrmann, M., and Rueckert, U., “Run-time reconfigurability in embedded multiprocessors”, ACM SIGARCH Computer Architecture News, vol. 37, pp. 30–37, 2009.

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