Publication Type : Conference Paper
Publisher : 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
Source : 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, Number EPFL-CONF-181610 (2012)
Keywords : Algorithm design and analysis, codecs, Complex algorithms, computational modeling, Decoding, Design space exploration, design time shortening, Field programmable gate arrays, FPGA, FPGAs, GPU, GPUs, Hardware, hardware designers, Kernel, LDPC decoder case, LDPC decoding, Logic design, logic simulation, low density parity check decoders, Microprocessor chips, multiparametric design space, multiplatform simulation, parallel computing, parity check codes, portable OpenCL golden model, public domain software, register transfer level, RTL, Silicon to Open CL, simulation tools, SOpen CL, unified multiplatform programming model
Campus : Bengaluru
School : School of Engineering
Department : Computer Science
Year : 2012
Abstract : Hardware designers and engineers typically need to explore a multi-parametric design space in order to find the best configuration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips need to explore parameters such as the optimal bit width and data representation. This is the case for the development of complex algorithms such as Low-Density Parity-Check (LDPC) decoders used in modern communication systems. Currently, high-performance computing offers a wide set of acceleration options, that range from multicore CPUs to graphics processing units (GPUs) and FPGAs. Depending on the simulation requirements, the ideal architecture to use can vary. In this paper we propose a new design flow based on Open CL, a unified multiplatform programming model, which accelerates LDPC decoding simulations, thereby significantly reducing architectural exploration and design time. Open CL-based parallel kernels are used without modifications or code tuning on multicore CPUs, GPUs and FPGAs. We use SOpen CL (Silicon to Open CL), a tool that automatically converts Open CL kernels to RTL for mapping the simulations into FPGAs. To the best of our knowledge, this is the first time that a single, unmodified Open CL code is used to target those three different platforms. We show that, depending on the design parameters to be explored in the simulation, on the dimension and phase of the design, the GPU or the FPGA may suit different purposes more conveniently, providing different acceleration factors. For example, although simulations can typically execute more than 3× faster on FPGAs than on GPUs, the overhead of circuit synthesis often outweighs the benefits of FPGA-accelerated execution.
Cite this Research Publication : G. Falcao, Owaida, M., Novo, D., Dr. Madhura Purnaprajna, Bellas, N., Antonopoulos, C. D., Karakonstantis, G., Burg, A., and Ienne, P., “Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case”, in 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012.