Publication Type : Conference Paper
Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017
Source : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, IEEE, Coimbatore, India (2017)
Url : https://ieeexplore.ieee.org/document/8524188
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2017
Abstract : Scan testing methodology called at-speed testing is very essential for delay fault testing. At-speed scan-testing method is further classified into two types namely, Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). LOC, a scheme mostly used to abate the test power consumption, is also known as broad-side test scheme, while LOS scheme used to improve transition fault coverage. Till the recent times, LOC and LOS has been widely investigated on single clock domain circuits regarding test power consumption and transition fault coverage respectively. In this paper, we proposed LOC and LOS test scheme for multiple clock domain circuits and investigated its power consumption and transition fault coverage. IWLS'05 opencores benchmark circuits, which include multiple clock domains, have been used in this work. Test analysis results demonstrate that test power reduces and transition fault coverage improved when test vectors are generated with LOC and LOS test scheme when compared to those generated using conventional ATPG tool.
Cite this Research Publication : S. Pandey, Dr. N.S. Murty, and Ranjan, R., “Test Power and Transition Fault Coverage Comparison between LOC and LOS Test Scheme for Multiple Clock Domain Circuits”, in 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017, Coimbatore, India, 2017.