Publications

Abstract : Due to advancement in the design technology of digital integrated circuits, the complexity of the circuit structure increases. As a result, the number of pins in a digital board also increases. Hence, the testing of the board’s input–output pins becomes difficult. Also, while manufacturing the board, if there is any fault, then it is going to affect the functionality of the board. Since FPGAs are widely used in critical applications such as military, avionics and medical devices, it is of utmost importance that testing of FPGA boards should be made so as to detect the faults and remove them before it is placed into a system. So, in this paper, an architecture which can test the input–output pins of an FPGA board (800 pins) and detect single stuck-at faults is proposed. The results were simulated in Xilinx ISE Design Suite14.4 using VHDL.