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Universal gates on garbled circuit construction

Publication Type : Journal Article

Publisher : Concurrency Computation

Source : Concurrency Computation, John Wiley and Sons Ltd (2019)

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Keywords : Boolean circuit, Circuit construction, Constant values, Cryptography, Efficiency, garbled circuits, Gate arrays, Logic gates, Row reductions, secure computation, Timing circuits, Universal gates

Campus : Bengaluru

School : Department of Computer Science and Engineering, School of Engineering

Department : Computer Science

Year : 2019

Abstract : Efficient garbled circuit construction can lead to more practical secure computation protocols. Garbled circuit construction has been considered as a separate goal for optimization as efficiency of the secure computation protocol is directly related to the efficiency of garbled circuit construction. Various optimizations such as, point-and-permute technique, free-XOR, garbled row reduction, and dual-key cipher are proved to make the garbled circuit construction efficient. In this paper, we propose garbled circuit construction with the universal gates; for demonstration purpose, we have considered NOR gates and shown optimization on circuit construction in two models. By the use of single type of gate, the gate array in the circuit representation is eliminated and a constant value is used in protocols. In addition, we have reduced the number of rows in garbled table to two rows per gate with two or zero encryption calls during garbled circuit construction and two or zero decryption calls during evaluation of garbled circuit. © 2019 John Wiley & Sons, Ltd.

Cite this Research Publication : A. A. T. Innocent, Sangeeta, K., and Dr. Prakash G., “Universal gates on garbled circuit construction”, Concurrency Computation, 2019.

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