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Variation-aware parameter based analog yield optimization methods

Publisher : Analog Integrated Circuits and Signal Processing

Campus : Bengaluru

School : School of Engineering

Department : Computer Science

Year : 2018

Abstract : pThe problem of yield estimation and optimization of analog circuits is addressed in this paper. Given convex design-space constraints that define the feasible region for the design, we first linearize the feasible region by approximating it with linear constraints. Using the linear constraints approximating the feasible region, we make primarily two contributions in this paper—first we use the concept of parameter importance, introduced in Naidu (20th International conference on VLSI design, 2007. Held jointly with 6th international conference on embedded systems. IEEE, pp 265–270, 2007) and expanded on in Kondamadugula and Naidu (ACM Great Lakes symposium on VLSI. IEEE, pp 452–457, 2016), to partition the design space variables into those that affect yield a lot, and those that have only a marginal impact, and then use this information to speed-up a Monte-Carlo method that searches for a high-yield design point. Specifically, a two-step sampling procedure is devised for the variables where the outer-most loop is dedicated to the “weak” variables while the inner loop is dedicated to the “strong” variables. Thus the given simulation budget is then disproportionately directed towards those design space parameters deemed more important. Since there are likely be only a few variables that impact yield greatly, we can choose to use low-dimensional quasi-Monte-Carlo sequences for sampling in the inner loop which is an added benefit of our technique. For each sample design point, the Monte-Carlo algorithm would need to calculate yield using the Cadence yield estimation tool. This is a costly procedure. For the second application of the concept of parameter importance, we propose a fast procedure for calculating yield that works with a linear approximation of the feasible region, and uses design space information to speed up the calculation of yield. We compare our methodology with the standard one using the Cadence circuit simulator environment in 180nbsp;nm technology and show that we obtain superior results in the same amount of simulation time. © 2018, Springer Science+Business Media, LLC, part of Springer Nature./p

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