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Publication Type : Journal Article
Publisher : Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering
Source : Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, Volume 108 LNICST, Chennai, p.242-245 (2012)
ISBN : 9783642356148
Keywords : Burrows Wheeler transform, Communication, Constant coefficients, Digital signal processing, Digital signal processing algorithms, Discrete wavelet transforms, Distributed arithmetic, DWT, Field programmable gate arrays (FPGA), Filter banks, Image and video coding, JPEG 2000, Look up table, Memory architecture, Motion Picture Experts Group standards, Multiply-and-accumulate, Network architecture, Novel methodology, Table lookup, VLSI implementation, Xilinx fpgas
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2012
Abstract : Multiply and accumulate function is the important part of digital signal processing algorithms. This can be implemented more effectively with distributed arithmetic (DA) architecture . These architectures make extensive use of look-up tables, which make them ideal for implementing digital signal processing functions on Xilinx FPGAs. An emerging arithmetic-intensive digital signal processing algorithm is the discrete wavelet transform (DWT) which have proven to be extremely useful for image and video coding applications like MPEG-4 and JPEG 2000. But the limitation of this architecture is that the size of look-up tables get increased exponentially as the constant coefficients of wavelet used for these applications increases. In this paper, we proposed a novel methodology to implement the Burrows wheeler transform (BWT)  block in FPGA for achieving memory reduced DA. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.
Cite this Research Publication : Remya Ajai A. S., Rajan, L., and Shiny, C., “VLSI implementation of Burrows wheeler transform for memory reduced distributed arithmetic architectures”, Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, vol. 108 LNICST, pp. 242-245, 2012.