Publication Type : Journal Article
Publisher : International Journal of Electronics Letters, Taylor & Francis.
Source : International Journal of Electronics Letters, Taylor & Francis, Volume 4, Number 1, p.38–49 (2016)
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2016
Abstract : This article presents hardware architecture for a video encoder that employs 3-D discrete cosine transform (3-D DCT) algorithm. The transform algorithm chosen for the implementation adapts entropy reduction technique and does not require the second transpose memory to store the coefficients of video cube. The implemented hardware architecture for 3-D DCT is verified for its functional specifications, and its performance evaluation is done on parameters such as power, area, and operating frequency with that of conventional architecture. The video encoder is built using 3-D DCT and other submodules and verified for its functionality.
Cite this Research Publication : G. Hegde, Dr. Shikha Tripathi, and Vaya, P. R., “VLSI implementation of the video encoder using an efficient 3-D DCT algorithm”, International Journal of Electronics Letters, vol. 4, pp. 38–49, 2016.