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About the Project

High-level synthesis (HLS) tools enable the use of high-level languages such as C, C++, and SystemC for VLSI design. This simplifies the programming task and allows the programmers to apply various pragmas or synthesis directives to control the hardware design parameters. Since these directives can take multiple values and be applied in many places for ASIC and FPGA designs, the design space grows exponentially, making the design space exploration time-consuming. Identifying the possible designs that simultaneously optimize the multiple conflicting objectives, such as area, latency, and power, has been one of the critical, challenging tasks in VLSI design.

Department and Campus

Amrita School of Computing, Bengaluru

Skillsets Preferred from Applicants

Basics of verilog or VHDL, Vivado or Catapult, Hardware Design and Synthesis Tool.

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