Back close

Time left
for the event

About the Workshop

Workshop on Cadence Online Tools Training

Department of Electronics & Communication Engineering, Amrita School of Engineering (Amritapuri, Kollam Campus) is organizing a 3-day Online Workshop Session of Cadence Tools from 28th to 30th July 2022 as a part of Workshop series given to our M.Tech VLSI students. Limited seats are made open for Research Scholars and UG/PG students who are working on similar Projects.  The topic of session is Cadence EDA tools for Full/ Semi Custom Design flow, Design for Test, Statis Timing Analysis. Detailed Program schedule can be found below.

Register if you are interested to attend (Limited Seats available). The meeting links and other details will be emailed to registered & selected participants.  Certificates will be provided based on attendance on all three days.

Speakers

Workshop on Cadence Online Tools Training
Anish Kumar

Sr.Application Engineer with Entuple,
10 year of experience in VLSI and Embedded Domain

Workshop on Cadence Online Tools Training
Priyanshu Datta

Field Application Engineer in Entuple Technologies Private Limited.

Workshop on Cadence Online Tools Training
Ms. Saraswati

PD Engineer – Cadence

Schedule

Day-1: July 28, 2022

Speaker : Anish K. Sharma, Sr. AE – Noida

Session-1: (10 am – 12 pm)

  • Introduction to IC Design Flow
  • Cadence EDA tools for Semi-Custom IC Design
  • Functional Simulation using Incisive tool.

(12pm-1pm) – Lab 1 – Self-practice by participants.

Session-2: (2 pm – 4 pm)

  • Introduction to TCL Scripting
  • RTL Synthesis using Genus Synthesis Solution
  • Synthesis Optimization for Power/Performance

(5pm-6pm) – Lab 2 – Self-practice by participants.

Demo: The sessions will be demonstrated by “UART/8-bit counter” as an example.

Day-2: July 29, 2022

Speaker : Priyanshu Datta, AE, Bangalore

Session-3: (10 am – 12 pm)

  • Introduction to Functional Verification
  • Functional Verification using Conformal LEC Tool
  • Pre & Post Synthesis Analysis.

(12pm-1pm) – Lab 3 – Self-practice by participants.

Session-4: (2 pm – 4 pm)

  • Introduction to DFT (Design For Test)
  • Synthesis based on DFT using Modus tool
  • ATPG Based DFT

(5pm-6pm) – Lab 4 – Self-practice by participants.

Demo: Sessions will be demonstrated by “Shift Register/Counter” as an example.

Day-3: July 30, 2022

Speaker : Ms. Saraswati, PD Engg – Bangalore

Session-5: (10 am – 12 pm)

  • Introduction to STA
  • Timing Analysis using Innovus
  • STA flow using TEMPUS tool

(12pm-1pm) – Lab 5 – Self-practice by participants.

Session-6: (2 pm – 4 pm)

  • Introduction to Low power
  • Power Analysis using VOLTUS
  • Basic flow using VOLTUS tool

(5pm-6pm) – Lab 6 – Self-practice by participants.

Demo: The sessions will be demonstrated by UART/8-bit Counter as an example.

M. Tech. in VLSI Design

Admissions Apply Now