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A 10-b 1-GHz 33-mW CMOS ADC

Publisher : IEEE Journal of Solid-State Circuits

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2013

Abstract : This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and corrects for the gain error. Using a one-stage opamp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with a signal-to-(noise+distortion) ratio of 52.4 dB, achieving a figure of merit of 97 fJ/conversion-step. © 1966-2012 IEEE.

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