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A new leakage power reduction technique for CMOS VLSI circuits

Publication Type : Journal Article

Publisher : Journal of Artificial Intelligence

Source : Journal of Artificial Intelligence, Volume 5, Number 4, p.227-232 (2012)

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Campus : Coimbatore

School : School of Dentistry

Department : Periodontics

Year : 2012

Abstract : A robust method, which is equally effectual for static power control in CMOS VLSI circuits for System on Chip (Soc) applications in deep submicron technologies is proposed. Referring1 to the International Technology Roadmap for Semiconductors (ITRS), the total power dissipation maybe significantly contributed by leakage power dissipation. To reduce leakage the proposed method introduces two self controlled stacked leakage control transistors (LT) between Vdd and ground, which offers high resistance, when it is in off state. The gate and substrate of each LT's are tied together to introduce Dynamic Threshold voltage MOSFET (DTMOS). This proposed method is intuitively momentous and leads to better performance measure in terms of dynamic power, leakage power propagation delay and Power Delay Product (PDP) with standard threshold devices. The experiment and simulation results show that the proposed method effectively outperforms than the base case with little area overhead. © 2012 Asian Network for Scientific Information.

Cite this Research Publication : M. Ga Priya, Baskaran, Kb, Krishnaveni, Dc, and Srinivasan, Sd, “A new leakage power reduction technique for CMOS VLSI circuits”, Journal of Artificial Intelligence, vol. 5, pp. 227-232, 2012.

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