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A novel leakage power reduction technique for CMOS VLSI circuits

Publication Type : Journal Article

Publisher : European Journal of Scientific Research

Source : European Journal of Scientific Research, Volume 74, Number 1, p.96-105 (2012)

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Campus : Coimbatore

School : School of Engineering

Department : English & Humanities

Year : 2012

Abstract : In recent years, with shrinking of device technologies, leakage power (static power) dissipation has become an inevitable proportion of the total power dissipation in an integrated circuit. The leakage power dissipation is projected to grow exponentially during the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices. In this paper a robust method which is equally effectual for static power control for CMOS VLSI circuits in deep submicron technologies has been proposed. It is also referred to as 'sleepy pass gate' uses two complementary sleep transistors connected in parallel forming a pass gate structure. In our leakage reduction technique, the exact output logic state is preserved in both active and standby mode of operation. Thus, experiments conducted with a range of process technologies on combinational logic gates and MCNC'91 benchmark circuits show that the proposed method gives significant savings in leakage power upto 2 orders of magnitude, with lesser area and delay penalty. © EuroJournals Publishing, Inc. 2012.

Cite this Research Publication : M. Ga Priya, Baskaran, Kb, and Krishnaveni, Dc, “A novel leakage power reduction technique for CMOS VLSI circuits”, European Journal of Scientific Research, vol. 74, pp. 96-105, 2012.

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