Abstract : Neuromorphic computing is an emerging architecture to address the issues of parallel computing like energy efficiency, size and speed. In standard neural network the basic computation is matrix multiplication between inputs to the neurons and their weights. This type of heavy computation can be handled conventionally with high end Graphics Processing Units (GPUs) effectively. The current technologies like Parallel CPUs and GPUs can provide parallel computation, but by incurring heavy computation and power consumption overheads. This has motivated research in hardware implementation of spiking neural networks with silicon technologies. The hardware implementation of event driven networks can drastically reduce the computational load and hence the power consumption. This survey paper discusses the various hardware implementations of spike neural networks (SNNs) and how they address different issues related to parallel computation of neural network functions. © 2006-2019 Asian Research Publishing Network (ARPN).