Publication Type : Conference Paper
Publisher : Springer Singapore
Source : Computational Advancement in Communication Circuits and Systems (Scopus), Springer Singapore, Singapore, p.305–312 (2020)
Url : https://link.springer.com/chapter/10.1007/978-981-13-8687-9_28
ISBN : 9789811386879
Keywords : CMOS, Fall Delay, Low Power, Rise Delay, Variable Delay
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2020
Abstract : Circuit designing of variable delay elements has been in practice for decades. However, these delay circuits have not been able to demonstrate equal rise and fall delays at its output. One of the major reasons for this failure is that the construction of delay circuits is non-symmetric. In this paper, we have attempted in designing a simple symmetric architecture which can produce the delayed output with almost identical rise and fall time. The proposed delay circuit is simulated using 90 nm GPDK in Cadence Virtuoso® initially for an input signal of 1 GHz at power supply Vdd\thinspace=\thinspace1.1 V, and the results infer that the contrast (Δ) in rise and fall time is very small even during the input variations.
Cite this Research Publication : Dr. Pritam Bhattacharjee and Alak Majumder, “A Variable Delay Circuit to Develop Identical Rise/Fall Time in the Output”, in Computational Advancement in Communication Circuits and Systems (Scopus), Singapore, 2020, pp. 305–312.