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Adaptive Block Pinning for Multi-core Architectures

Publication Type : Journal Article

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Abstract : pDifference between speed of processorand memory is increasing with advent of everynbsp;new technology. Chip Multi Processors (CMP)nbsp;have further increased the load on the memorynbsp;hierarchy. So it has become important to managenbsp;on-chip memory judiciously to reduce averagenbsp;memory access time. The previous research hasnbsp;shown that it is better to have a shared cache atnbsp;the last level of on-chip memory hierarchy.nbsp;Sharing last level of cache gives rise to a newnbsp;category of cache misses; those were not presentnbsp;in uniprocessor, called “inter-processor misses”.nbsp;This paper proposes a technique to eliminatenbsp;inter-processor misses by giving replacementnbsp;ownership of a block to a processor who broughtnbsp;it into the cache. This reduction in interprocessornbsp;misses, which constitutes 40% of overnbsp;all misses, will result in performancenbsp;improvement. Also two different ways ofnbsp;relinquishing the ownership of a block are beingnbsp;proposed, so that if some other processor, othernbsp;than owner, can make use of the block in a morenbsp;efficient way, ownership will be transferred to thenbsp;new processor./p

Cite this Research Publication : R. Kumar, Chaturvedi, N., and Sudarshan, T. S. B., “Adaptive Block Pinning for Multi-core Architectures”.

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