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An 8 Bit 4 GS/s 120 mW CMOS ADC.

Publisher : Journal of Solid-State Circuits

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Verified : Yes

Year : 2014

Abstract : A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dBand a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

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