Publication

Abstract : This paper presents object-oriented testbench architecture for APB based AHB interconnect which is based on universal verification methodology (UVM) to build an efficient and structured verification environment. UVM-SV based AHB System that follows AHB Protocol, consists three AHB master, four AHB slave, an AHB interconnect (Design Under test) and one APB configure model which communicate with each other on the AHB bus and APB configure model decodes slave address range and generates signals for slave selection reduces interface complexity. System verilog interfaces in the testbench and DUT and virtual interfaces in the class based test environment cannot make use of type parameterize, results in very cumbersome code. To overcome this problem, this paper is using approach of pushing the virtual interface into the configuration database from top-level using uvm_config_db to reuse verification test environment and APB based AHB interconnect functional model is implemented which is configured as UVM component from testbech using uvm_config_db. A uvm_config_db method allows reuse of UVM components easily and configures uniformly. This paper is showing how APB based AHB Interconnect testbench is build using a uvm_config_db. The simulations are done using Mentor Graphics advanced Questasim 10.0b simulator with UVM base class library version 1.1d. © International Science Press.