Publication Type : Journal Article
Publisher : Advances in Intelligent Systems and Computing
Source : Advances in Intelligent Systems and Computing, Springer Verlag, Volume 394, p.429-441 (2016)
Url : http://www.scopus.com/inward/record.url?eid=2-s2.0-84959171639&partnerID=40&md5=2725520ea2e67b4724b59693cf2bbdca
ISBN : 9788132226543
Keywords : Artificial intelligence, Computer architecture, Design and evaluations, Electric power transmission networks, integrated circuit design, latency, Mesh generation, Network architecture, Network simulator NS-2, Network-on-chip, Network-on-chip architectures, On chip communication, Partial mesh, Quality of service, Redundant connections, Routers, Semiconductor device manufacture, semiconductor technology, Servers, Throughput, Topology, VLSI circuits
Campus : Coimbatore
School : School of Engineering
Center : Center for Computational Engineering and Networking, Computational Engineering and Networking
Department : Wireless Networks and Applications (AWNA), Center for Computational Engineering and Networking (CEN), Mathematics
Year : 2016
Abstract : The importance of on-chip communication interconnects was greatly highlighted with the advent of semiconductor technology at nanoscale domain. As the sizes of semiconductor features are reduced day by day, there occurred problems related to wiring. Network-on-Chip architectures are therefore implemented to overcome the wiring issues and have lately been considered as an important area for research. The communication on NoC is carried out in specific topologies by means of routers. In this paper, Partial Mesh of Grid topology (PMG) is considered. We use the Quality of Service (QoS) mechanism to minimize the area and power. PMG-based NoC will give minimum area and power and it reduces the high chances of redundant connections. Throughput and latency are analysed along with other parameters like packet loss ratio and jitter using network simulator NS-2. Area and power analyses are done using Synopsys Design Compiler and PrimeTime PX tool. Our experimental results show that the architecture with QoS mechanism gives a significant reduction in area and power when compared to Region-based Routing (RBR) mechanism. Moreover, the partial mesh of grid topology gives minimal latency and high throughput when compared to mesh of grid topology. © Springer India 2016.
Cite this Research Publication : P. Mohan, Dr. Somasundaram K., Dash, S. S., Das, S., and Bhaskar, M. A., “Design and evaluation of 3D NoC routers with quality-of-service (QoS) mechanism for multi-core systems”, Advances in Intelligent Systems and Computing, vol. 394, pp. 429-441, 2016.