Publication Type : Conference Paper
Publisher : IEEE
Source : 2022 IEEE International Test Conference India (ITC India), 2022, pp. 1-4, doi: 10.1109/ITCIndia202255192.2022.9854556
Url : https://ieeexplore.ieee.org/document/9854556
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2022
Abstract : In this paper, a programmable low power linear feedback shift register for BIST applications has implemented in Xilinx Vivado Suite 2019. The design is parameterizable for 'n-bit’ polynomials and the seed value of user choice. Moreover, the design has a unique methodology of forcing low signal 0s in the dissimilar vector bits before the switching transition of registers and as well as incorporating the combination of two stage LFSRs (DT-LFSR) which could successfully reduce the number of output vector transition by ~70% with respect to the conventional LFSRs and hence significant reduction in dynamic power due to switching activity between adjacent vectors. The design has synthesized and simulated for 4,8-,16-,32- and 64-bit LFSR of different polynomials
Cite this Research Publication : M. B, G. Remadevi and R. Bakthavatchalu, "Design of a Programmable Low Power Linear Feedback Shift Register for BIST Applications," 2022 IEEE International Test Conference India (ITC India), 2022, pp. 1-4, doi: 10.1109/ITCIndia202255192.2022.9854556