Abstract : Hardware Trojans (HT) have become a serious security concern for semiconductor industries due to the rise in outsourcing of the fabrication of ICs. Fabrication foundries with minimal security pave an easy way for the adversary to tamper the IC design and place a malicious circuit of his interest into the IC. Detection of these malicious circuits is also becoming increasingly difficult due to a large variety of trojans, increase in their complexity and their stealthy nature. An effective Hardware Trojan detection algorithm using a signal processing technique called Compressive Sensing (CS) is proposed in this work. This method mainly focuses on test vector reduction which greatly reduces the test time during the detection process. This compression of test vectors is done using Compressive Sensing (CS). Key nodes in the selected ISCAS ’85 circuits are identified by computing Transition Probability (TP) of each node in the circuit. The circuits with trojans inserted in the key nodes are subjected to further non-destructive analyses to detect the presence of trojan(s). Also, metrics such as True Positive Rate (TPR) and Probability of Detection (PD) are validated to analyse the efficiency of the proposed algorithm © Springer Nature Singapore Pte Ltd. 2019.